
`include "common_header.verilog"

//  *************************************************************************
//  File : pause_qtimer_64
//  *************************************************************************
//  This program is controlled by a written license agreement.
//  Unauthorized Reproduction or Use is Expressly Prohibited.
//  Copyright (c) 2014 MoreThanIP.com, Germany
//  Designed by : Daniel Koehler
//  info@morethanip.com
//  *************************************************************************
//               Ethernet MAC Core
//  *************************************************************************
//  Description: Create pulse when quanta time has expired (512bit).
//               Configurable assuming clock enable either runs on 64-bit words
//               or on 8-bit words.
//  Version    : $Id: pause_qtimer_64.v,v 1.2 2015/01/14 21:25:35 dk Exp $
//  *************************************************************************

module pause_qtimer_64 (
   reset,
   clk,
   clk_ena,
   qinc8,
   qtime,
   qtime_run);

input   reset;          //  Async Active High reset
input   clk;            //  Clock
input   clk_ena;        //  Clock enable
input   qinc8;          //  Increment by 8 per clock enable (i.e. word clock enable), else only by 1 (i.e. byte clock enable)
output  qtime;          //  pulse when pause time of 1 quanta expired (512 bits)
input   qtime_run;      //  timer is enabled, should generate pulses

reg     qtime;
reg     [5:0] scnt;     //  64*8-bit = 512 bit time
wire    [6:0] scnt_next;//  with carry

assign scnt_next = (qinc8==1'b 1) ? {1'b 0, scnt} + 7'd 8 : // weight clock enable step with 8
                                    {1'b 0, scnt} + 7'd 1;  // or only 1

always @(posedge reset or posedge clk)
   begin : process_1
   if (reset == 1'b 1)
      begin
      scnt <= 6'd 0;
      qtime <= 1'b 0;
      end
   else
      begin
      //  CLOCK ENABLE
      if (clk_ena == 1'b 1)
         begin
         //  scaler
         //  ------
         if (qtime_run == 1'b 1)
            begin
            scnt <= scnt_next[5:0];
            end
         else
            begin
            //  reset counter if not enabled
            scnt <= 6'd 0;
            end
         end

      //  create pulse every 512bit time
      //  ------------------------------
      if (scnt_next[6] == 1'b 1 & clk_ena == 1'b 1)
         begin
         qtime <= 1'b 1;
         end
      else
         begin
         qtime <= 1'b 0;
         end
      end
   end


endmodule // module pause_qtimer_64
